The present invention relates to a digital-to-analog converter which is suitable for use in the semiconductor integrated circuits and the like.
FIG. 3 shows an example of the digital-to-analog converter (hereinafter, simply referred to as a D/A converter). Herein, 3 designates a D/A converter as a whole, wherein an input digital signal is converted into an analog signal to be outputted. In general, this D/A converter 3 is configured by the CMOS integrated circuits, and this type of D/A converter is called a resistance-dividing-type converter.
Next, 4 designates a decoder which has three inputs and eight outputs. More specifically, three inputs of this decoder 4 are respectively designated by numerals "I30", "I31", "I32", to which signals S30, S31, S32 are respectively supplied. Herein, the signals S30, S31, S32 respectively correspond to three bits which are disposed in a digit-place-ascending order of the predetermined binary notation, so that the signal S30 corresponds to the bit of the lowest digit position, while the signal S32 corresponds to the bit of the highest digit position. Similarly, eight outputs of the decoder 4 are respectively designated by numerals T30, T31, T32, T38, T34, T35, T36 and T37 which respectively correspond to eight bits in a digit-place-ascending order of the predetermined binary notation. In response to the combination of the digits (i.e., 0 or 1) which are respectively applied to three inputs I30-I32 of the decoder 4, one of the outputs T30 through T37 is selected. Incidentally, this combination of the digits applied to three inputs I30-I32 of the decoder 4 will be represented by a signal value "va13". When one of the outputs T30-T33 is selected, a signal having a high logical level (hereinafter, simply referred to as a 1-level signal) is outputted. On the other hand, when one of the other outputs T34-T37 is selected, a signal having a low logical level (hereinafter, simply referred to as a 0-level signal) is outputted.
Next, F30 through F37 designate field-effect transistors (i.e., FETs). Among them, F30 through F33 designate n-channel FETs which are formed on a p-well region surrounded by a dotted line P3 in FIG. 3. Normally, the 0-level signal is applied to each of the gates of the FETs F30 through F33. When the 1-level signal is applied to the gate, each of these FETs is set in an on-state. On the other hand, F34 through F37 designate p-channel FETs, which are formed on a n-well region surrounded by a dotted line n3 in FIG. 3. Normally, the 1-level signal is applied to each of the gates of the FETs F34 through F37. When the 0-level signal is applied to the gate, each of these FETs is set in an on-state. FIG. 4 shows an example of the construction of the field-effect transistors, wherein a numeral 4a represents the n-channel FET (i.e., F30-F33), while another numeral 4b represents the p-channel FET (i.e., F34-F37).
In FIG. 3, 30-37 designate resistors; E3 designates a power-voltage terminal; and GND3 designates a ground terminal. The resistors 30-37 are arranged to be related with the FETs F30-F37 respectively. Normally, the voltage of "+SV" is applied to the terminal E3. Therefore, the potential is equal to +2.5V at a point PT3 which is positioned among the FET F34 and resistors 33, 34.
In FIG. 3, a numeral "out3" designates the output signal of the D/A converter 3.
In the D/A converter 3 having the above-mentioned configuration, when the foregoing signal value va13 is set at the predetermined value represented by a 3-bit binary code "000", the output T30 of the decoder 4 is selectively activated so that its signal level is put on the logical level 1, resulting that the FET F30 is selectively turned on. At this time, the voltage at the terminal GND3 is applied to the output signal out3.
In the meantime, when the signal value va13 is set at another value represented by a binary code "100", the output T34 of the decoder 4 is turned to be at the logical level 0, resulting that the FET F34 is turned on. Since the potential difference (normally, 5V) applied between the terminals E3 and GND3 is equally divided by eight resistors 30-37, the voltage of 2.5V is ideally applied to the output signal out3.
Meanwhile, in the aforementioned D/A converter 3, the resistors 30-33 are positioned on the p-well region, while the other resistors 34-37 are positioned on the n-well region. However, in the D/A converter, there exists a deviation (or unstableness) among the resistance values of the resistors 30-33 and the resistors 34-37. This means that the desirable resistance values cannot be obtained with accuracy because of the following two reasons.
Firstly, there is formed a gap (or stage difference, i.e., height difference) between the p-well region and n-well region (see FIG. 4). The formation of the gap results from the characteristic of the silicon dioxide region, such as LOCOS (i.e., Local Oxidation of Silicon), which is provided between the p-well region and the n-well region. The gap is used for aligning the mask on the semiconductor wafer. In short, the gap is an essential element for the photolithography process. As a result, even if the width of the pattern on the reticle is the same, there must be occurred a small difference between the widths of the resistance patterns by the so-called multireflection effect which is occurred at the inside of the film when performing the photolithography technique in the manufacturing process. Thus, the resistors on the p-well region are formed at the higher positions (or lower positions) as compared to the resistors on the n-well region. When such height difference among the resistors is relatively large, the resistance values of the resistors formed on the p-well region become higher than those of the resistors formed on the n-well region, and consequently, it becomes impossible to obtain the accurate analog output. Such difference (or disparity) between the resistance values of the resistors is frequently occurred particularly in the gap portion. FIG. 5 is a graph showing the resistance values of the resistors 30-37 in connection with the positions of the resistors formed between the ground terminal GND3 and the power-supplying terminal E3. As is understood from the graph shown in FIG. 5, each of the resistance values of the resistors 30-33 and 34-37 changes at a point PT3. In FIG. 5, a difference between the resistance values is represented by ".DELTA.E1". As described before, such difference between the resistance values may deteriorate the characteristic of the D/A converter. In FIG. 6 showing a relationship between the digital input and the analog output of the D/A converter, a solid line represents an actual characteristic, while a dotted line represents an ideal characteristic which must be illustrated by a linear curve. As shown in FIG. 6, the actual characteristic is deviated from the ideal characteristic. Herein, the maximum deviation is represented by ".DELTA.Ea" which corresponds to ".DELTA.E1" representing the difference between the resistance values. In short, there is a drawback in that the sufficient precision for the linear D/A conversion characteristic cannot be obtained.
Secondly, there is a certain distribution of the resistance values of the resistor pattern on the surface of the wafer. An example of such distribution manner is shown by a graph of FIG. 2A. Such uneven thickness of the thin film in which the resistor patterns are manufactured results in the above-mentioned distribution of the resistance values caused by the manufacturing process to be actually carried out. Therefore, the resistance values for the D/A converter 3 are gradually reduced in the right-side positions as shown in FIG. 2A, for example. According to such distribution of the resistance values, the resistance value of the resistor 30 is the highest among the resistors 30-37; the resistance values of the resistors 31, 32 are lower than the resistor 30; the resistance values are gradually reduced in the resistors 30-37; and the resistance value of the resistor 37 is the lowest. In FIG. 2A, ".DELTA.Eb" represents a difference among the resistance values due to the uneven thickness of the thin film in the resistor pattern. Such difference among the resistance values may deteriorate the characteristic of the D/A converter. In FIG. 2B showing a relationship between the digital input and the analog output of the D/A converter, a solid line represents an actual characteristic of the D/A converter, while a dotted line represents an ideal characteristic of the D/A converter which is represented by a linear curve. As shown in FIG. 2B, the actual characteristic deviates from the ideal characteristic. The maximum deviation between them can be represented by .-+..DELTA.Eb/2", for example. When the disparity of the resistance values of the resistors 30-37 is relatively large, it is not possible to set the level of the output signal out3 at the predetermined level with accuracy. For this reason, there is a drawback in that the sufficient linear D/A conversion characteristic cannot be obtained.